The present invention relates to electronic comparators in general, and more particularly to an improved latching type comparator.
In radars and ECM systems and the like, analog input data is generally gathered over very small intervals of time, like on the order of a millisecond or so. Modern systems of this type tend to divide the input data interval into much smaller data samples, and convert these analog data samples into digital numbers representative thereof for post processing purposes in a digital signal processor or digital computer. A high speed analog-to-digital (A/D) converter is used for the conversion operation. The current trend is to require these A/D converters to have increasingly higher conversion rates and greater resolution (i.e. more bits in the converted digital word).
Normally, the basic building block of this type converter is of the "parallel" or "flash" type variety in which a bank of 2.sup.N -1 comparators compare the analog input signal to a series of reference voltages usually generated by a reference ladder resistor network with 2.sup.N -1 taps. In this manner, each analog signal sample is converted into a thermometer coded word appearing at the output of the bank of comparators. Each thermometer coded word may then be converted to another digital code, like a gray or binary code as the case may be, using appropriately chosen logic circuitry.
The number of comparators required in the type of converter just described is based on the bit resolution required thereof. For example, for a 3-bit converter, 7 comparators are needed; and for a 4-bit, 15 comparators are needed. Theoretically, the number of comparators required doubles with each 1-bit increase in resolution. Therefore, because of the shear numbers of comparators required for a reasonable number of bits of resolution, much emphasis is placed on the design of the comparator. Key features which are primarily considered include highspeed, low power, large analog input voltage range, ECL compatibility of latch clock inputs, and surface area of silicon substrate needed to implement the comparator bank in a semiconductor monolithic form. An improvement in any or all of these key areas will in effect be multiplied by the number of comparators used.
One type of high speed latching comparator suitable for use in a flash or parallel variety A/D converter, supra, is described in U.S. Pat. No. 4,147,943, issued Apr. 3, 1979 to James G. Peterson. This type comparator makes use of a gain stage to amplify the difference between the analog voltages being compared at the input stage when the comparator is in a follow mode, and a latching stage to sustain the output voltage independent of the analog input voltages when the comparator is in a latch mode. The latch and follow modes are selected exclusively by a switching circuit governed by input clocking signals. More particularly, the switching circuit renders the gain and input stages operative concurrently by drawing current therefrom to a single fixed current drain when the follow mode is selected, and renders the latching circuit operative by drawing current therefrom to the same current drain when the latch mode is selected.
One drawback of this type comparator is that the input stage is rendered inoperative during the latch mode. Time is wasted in returning the input stage to an operational state when the follow mode is reselected which, in effect, increases the response time in the process of sampling input signal comparisons. Another drawback is that the output lines are provided to the latching circuit directly. These output lines are generally relatively long and include a proportional amount of distributed capacitance. The line capacitance may cause a slower response in the comparator outputs to the comparisons occurring at the input stage thereof. In other words, time is wasted in the charging and discharging of the line capacitance creating a response delay between the input and output of the comparator. Under these conditions, the outputs may not always be in a state to represent accurately the comparative input state when the latch mode is selected. These and other undesirable features of the present comparators are believed improved upon by the inventive aspects of Applicants' comparator embodiment.